Yield is a key performance metric in the fabrication of semiconductor integrated circuit (IC) components used in modern electronic devices. ICs have intricate nanometer scale structures to perform high speed processing. These nanometer scale structures need be fabricated precisely. A deviation from tolerable limits of excursion during fabrication could cause anything between performance degradation to a complete failure of ICs. Fabrication of ICs involve hundreds of steps that span a several weeks. Yield is defined as the ratio of number of ICs that meet performance targets to the total number of manufactured ICs. An important goal in semiconductor fabrication is to maximize yield. To maximize yield, it crucial to identify and eliminate root causes of problems that affect yield. Measuring yield numbers at the end of IC fabrication, although necessary, is often not sufficient for identifying root causes of problems because of the extensive number and the complexity of steps involved in semiconductor fabrication. In order to identify root causes more effectively, semiconductor wafers are inspected for abnormalities or defects throughout the fabrication process, often after each significant process step. By inspecting for yield-affecting defects at a number check points, root causes of problems could be more readily identified and eliminated.
Dark-field wafer inspection is a widely used traditional method for detecting defects on wafers. In a dark-field wafer inspection tool, a laser beam is incident on the surface of a wafer to illuminate a tiny spot. Most of the laser beam undergoes specular reflection because semiconductor wafers are very smooth. An infinitesimally small amount of light—a few photons out of a million incident photons—is scattered when a defect is present in the region of wafer illuminated by the spot. A collection optic with a large numerical aperture collects scattered radiation and focuses the radiation on a detector. The electrical signal from the detector is analyzed to determine the presence of a defect in the region of wafer under the tiny spot. In order to inspect the entire surface area of the wafer, the wafer is scanned relative to the spot sequentially. Since the size of the spot is very small in comparison to the area of wafer surface, about a billion different points of the wafer are often sequentially scanned to inspect the entire surface of the wafer. While such scanning is an inherently slow process, efforts are often made to speed up scanning by moving the surface of the wafer at a very high speed.
With every new generation of semiconductor fabrication technology, the size of IC components have been becoming smaller. The reducing size of IC components also reduces the size of defects that affect yield. This is because the structures in ICs are sensitive to defects whose sizes are at least as big as the structures. Consequently, wafer inspection tools are expected to improve their defect sensitivity performance at the same rate as the shrinking of IC structures. Unfortunately, wafer inspection tools have not been keeping up. In the last ten years, while the smallest IC structures shrank from 130 nm to 14 nm (over 9× reduction), defect sensitivity improved from 50 nm to 20 nm (2.5× reduction). As a result, yield of modern ICs have been suffering.
In addition to demanding improved defect sensitivity, semiconductor fabrication also requires wafer inspection tools to have a high inspection throughput. Throughput refers to the number of wafers inspected per hour. In other words, semiconductor fabs desire to achieve maximum defect sensitivity by spending minimum amount of time for inspecting a wafer. Unfortunately, in traditional wafer inspection tools, sensitivity and throughput are opposing entities that exhibit a trade-off. In these tools, an increase in sensitivity decreases throughput, and an increase in throughput decreases sensitivity. This is because a throughput increase in traditional tools increases scanning speed; reduces scanning time per wafer; decreases scattered light energy; and decreases defect sensitivity.
The requirement to scan a tiny spot on a large wafer area originates because of the small field of view of a traditional wafer inspection system. The small field of view constraint is primarily a practical consequence of having a collection optic with a large numerical aperture required to capture radiation scattered in a wide range of polar and azimuthal angles.
A number of drawbacks are present in traditional wafer inspection tools, including: a) reduced throughput; b) reduced sensitivity; c) trade-off between sensitivity and throughput; d) complex high-speed scanning requirement; e) trade-off between field of view and numerical aperture; f) wafer deformation due to high-speed scanning; and g) reduced reliability due to components moving at high speeds.
Accordingly, there is a need for an improved wafer inspection system that can increase throughput; increase sensitivity; relax dependence of sensitivity on throughput; relax high-speed scanning requirement; relax the trade-off between field of view and numerical aperture; minimize wafer deformation; and increase reliability.